Time-to-Digital Converter IP-Core for FPGA at State of the Art
The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time–Mode (TM) circuits almost unfeasible.In particular, in Programmable Logic (PL) devices, such as FPGAs, the operation of the logic is usually synchronous with the system clock.However, it can